1. Field of the Invention
This invention is directed to a floating point processor circuit and the CPU interfaced with it, in general, and to a circuit which performs a square root function, in particular.
2. Prior Art
Many computer devices include a floating point processor as a portion thereof. The floating point processor can be operated to perform add, subtract, multiply, divide, and, sometimes, square root functions. Typically, the square root function, as performed by existing circuitry, is quite slow or requires extensive hardware components. Typically, the existing circuitry utilizes the Heron Iteration Process which is inherently slow as described hereinafter. Consequently, in order to enhance the speed of operation of existing circuitry, it is highly desirable to perform the square root function with circuitry which is both fast and economical.